| Title |
High-performance Low-area Iterative BCH Decoder Architecture for Ultra High Speed Optical Communications |
| Authors |
최대현(Dae-Hyun Choi) ; 이한호(Hanho Lee) |
| DOI |
https://doi.org/10.5573/ieie.2019.56.1.29 |
| Keywords |
Forward error correction ; BCH code ; Decoder ; Interleaving ; Modified step-by-step |
| Abstract |
This paper shows a 20% overhead-based iterative Bose-Chaudhuri-hocquenghem (BCH) code and a high-performance iterative BCH (I-BCH) decoder architecture for next generation optical communication systems with data rates of 100 Gbps or higher. The proposed I-BCH decoder architecture shows high error correction capability as well as high data throughput. The proposed 7-iterative I-BCH decoder adopts a memory-based interleaving technique and provides a net coding gain (NCG) performance of 10.25 dB based on 10 -15 post-FEC Bit Error Rate (BER) in 7 iterative decoding. The proposed high-performance I-BCH decoder architecture is synthesized using a 90-nm CMOS process. The performance of the proposed I-BCH decoder is 430 MHz and data rate of 165 Gbps in case of two parallel designs. Therefore, the proposed architecture can be applied to the next generation BCH-based forward error correction architecture with data throughput rate of 100Gbps or more. |