| Title |
High Level Leakage Power Modeling based on Static Probability of Primary Inputs |
| Authors |
김종규(Jonggyu Kim) ; 이준환(Joonhwan Yi) |
| DOI |
https://doi.org/10.5573/ieie.2019.56.2.58 |
| Keywords |
low power design ; leakage power ; power modeling ; static probability ; high level power analysis |
| Abstract |
The threshold voltage is lowered, the degree of integration of the chip is increased, and the leakage power is greatly increased as the temperature is increased. In this paper, we propose a leakage power modeling technique that can quickly analyze leakage power at a high level. We have shown that the leakage power can be predicted based on the input static probability using the fact that the leakage power varies accoding to the gate input value. It also extends to circuits with multiple gates to demonstrate practicality. For the n-input circuit, the process of deriving the problem of the expression of the leakage power model as a 2n coefficients will be described as a model using only n+1 coefficients. Also, we propose a method to make training input vector to be constant in modeling, so that the accuracy of power model is not dependent on training input vector. Experimental results show that the average accuracy of the power model is 98% and the average speed improvement is 218 times. |