| Title |
A Test Data Generation Method for 3-Dimensional Memory Semiconductors |
| Authors |
홍찬의(Chaneui Hong) ; 안진호(Jin-Ho Ahn) |
| DOI |
https://doi.org/10.5573/ieie.2019.56.3.24 |
| Keywords |
Memory test ; 3D memory test data generation ; March test ; RPCT |
| Abstract |
Most memory test algorithms repeatedly read or write memory cells by address to detect memory faults such as stuck-at, coupling, transition, pattern-sensitive, data retention faults, and so on. In this paper, we propose a memory test data generation technique that can effectively reduce the number of channels between the ATE and the memory to be tested using the characteristics of the memory test mentioned above. The proposed method converts address and data bus between ATE and memory test interface pins to serial form in test mode, and adds serial-parallel conversion logic on the base die of 3D memories. Applying the proposed architecture to a 512Mb memory can reduce the number of test interface pins by about 60%. Furthermore, the number of memories simultaneously tested using the same test channel size of an ATE can be increased by about 1.24 times. |