| Title |
Design of High-Performance Transform Circuit for 3D-HEVC Depth Map Intra Coding |
| Authors |
조경순(Kyeongsoon Cho) ; 권용욱(Yongwook Kwon) |
| DOI |
https://doi.org/10.5573/ieie.2019.56.9.32 |
| Keywords |
DCT, RD cost, Intra coding, Depth map, 3D-HEVC |
| Abstract |
he 3D-HEVC synthesizes intermediate views using two or more views and each view consists of texture and depth map. This paper proposes the architecture of high-performance 2D DCT circuit for the real-time intra coding of depth map. In the process of intra coding of depth map, the candidate modes up to 8 or 13 are selected per PU block and the transform operations are performed for each mode. The RD cost is estimated for each mode and the best mode is finally determined. Therefore, we need a circuit to perform the transform operations at the rate of more than 3.23 GPPS for all PU sizes for the real-time processing of 3,840x2,160 UHD images. The proposed circuit in this paper can transform the residual data for the candidate PU blocks stored in the RD list into the frequency domain at the rate of 32 pixels per cycle using parallel architecture, pipeline technique and efficient usage of transpose memory. The throughput of the synthesized circuit using 130nm standard cell library is 4.04 GPPS for each of 4x4, 8x8, 16x16, 32x32 DCT types with the maximum operating frequency of 126.26MHz, which satisfies the target performance of 3.23 GPPS for the real-time intra coding. |