| Title |
A Design of SIMT-based MapReduce Accelerator Architecture for Solid-state Drives |
| Authors |
정원섭(Won Seob Jeong) ; 노원우(Won Woo Ro) |
| DOI |
https://doi.org/10.5573/ieie.2019.56.10.25 |
| Keywords |
MapReduce acceleration; In-storage processing; SIMT architecture; Solid-state drive |
| Abstract |
MapReduce programming model is widely used to analyze large scale data in parallel. MapReduce programming acceleration technique using GPGPU has been studied to achieve high computing performance. However, the performance improvement of the MapReduce acceleration with GPGPU can be limited to the data transfer bandwidth between storage and host system. In this paper, we propose MapReduce accelerator architecture, which performs given map and reduce within solid state drive. Our accelerator architecture exploits a computing unit which is the extension of single instruction multi thread (SIMT) architecture. The unit includes additional execution pipeline for reduction-based MapReduce execution and a new instruction for the pipeline. Multiple SIMT units process data near the flash channels in parallel and each unit pipelines the execution of reduction-based MapReduce in two stages to hide flash memory access latency; Raw data buffering & Map and Reduce. The performance improvement is evaluated by GPGPU-Sim and our accelerator achieves 1.41 times higher processing throughput than a discrete GPU. |