| Title |
Offset Cancellation Comparator with Dynamic amplifier |
| Authors |
홍지윤(Jiyoon Hong) ; 김진태(Jintae Kim) |
| DOI |
https://doi.org/10.5573/ieie.2019.56.10.32 |
| Keywords |
Offset cancellation; Comparator; Dynamic-amplifier |
| Abstract |
In this paper, we present a study on a dynamic-amplifier based offset cancellation comparator that achieves both low offset and high energy efficiency. The proposed comparator cancels random transistor offset using dynamic preamplifier instead of conventional class-A amplifier to minimize power consumption. In contrast to digital offset calibration, the proposed comparator does not have to calibrate prior to normal operation. The proposed circuit was designed using a 28nm CMOS process and 1-sigma offset voltage found by Monte Carlo simulations is σ=10.6[mV]. In comparison, the conventional comparator with comparable power consumption shows 1-sigma offset voltage is σ=15.1[mV], verifying that the proposed circuit improves both power and area efficiency. |