| Title |
Behavioral Linearity and Noise Modeling for Dynamic Amplifiers |
| Authors |
김선경(Byongwook Yoo) ; 김진태(Sang-Soo Han) |
| DOI |
https://doi.org/10.5573/ieie.2019.56.12.17 |
| Keywords |
Dynamic Amplifier ; Behavioral Modeling ; Pipelined SAR ADC ; |
| Abstract |
This paper introduces the behavioral model of dynamic amplifier designed in 28nm CMOS process. First, the gain of the dynamic amplifier is analyzed from various pers0pectives, such as input common mode voltage, input differential mode voltage and pulse width. Next, the method to implement the gain value non-linearity model of the amplifier and the noise model through simulations is described. The gain model including nonlinearity exhibits -6.7%∼5.4% of modleing error and the noise model shows -11.2%∼13.5% of modeling error. The proposed model was applied to the 1.1Gs/s 7-bit pipelined ADC design verification to confirm the reliability and design efficiency of the proposed behavioral model. |