| Title |
Design of Phase Locked Loop for W-band Detection Transceiver |
| Authors |
김수정(Soo-Jeong Kim) ; 이석희(Suk-Hui Lee) ; 안광호(Kwang-Ho Ahn) ; 김완식(Wansik Kim) ; 정주용(Jooyong Jung) ; 이주영(Juyoung Lee) ; 서미희(Mihui Seo) ; 김소수(Sosu Kim) ; 김기진(Ki-Jin Kim) |
| DOI |
https://doi.org/10.5573/ieie.2020.57.1.28 |
| Keywords |
PLL ; Frequency synthesizer ; VCO ; Phase noise. ; |
| Abstract |
This paper reports a fractional-N phase locked loop(PLL) frequency synthesizer for W-bnad detection transceiver. PLL is implemented in 0.65nm CMOS process. PLL is consist of Phase Frequency Detector(PFD), loop filter, Voltage Controlled Oscillator(VCO), Multi-Modulus Divider(MMD), Delta Sigma Modulator(DSM). VCO has been designed with a LC resonant circuit to provide low power consumption & better phase noise. To make low the glitch level, add feedback loop to charge pump. MMD has consist of 1/2 divider and 8/9 prescaler. MMD can get the desired N in conjunction with 1-1-1 MASH DSM. The measured result show PLL has a output frequency range of 8.85 ∼ 9.6 GHz and 0 dBm output power. Phase noise of PLL is -110 dBc/Hz at 1 MHz offset frequency. |