| Title |
Low-Complexity Inference Accelerator for Binarized Convolutional Neural Networks |
| Authors |
최경찬(Gyungchan Choi) ; 신지훈(Jihoon Shin) ; 김태환(Tae-Hwan Kim) |
| DOI |
https://doi.org/10.5573/ieie.2020.57.1.53 |
| Keywords |
BCNN ; Inference accelerator ; FPGA ; Embedded system ; Low complexity ; |
| Abstract |
This paper proposes a low-complexity processor that accelerates the inference of the binarized convolutional neural networks. The proposed processor performs overall inference by the block, whose processing steps are convolution, binarization, and pooling. Each block is formulated to have a binary input and binary output, so that additional buffers to store inter-step temporary results can be eliminated effectively. The proposed processor processes each block by decomposing it to multiple 1×1 convolutions, thereby accelerates any blocks including convolutional layer and fully-connected layer, in a consistent way. It is implemented on Cyclone V FPGA with only 1.05 K adaptive logic module (ALM) and 2304 Kbit on-chip memory, showing the complexity efficiency of 22.514 GOP/s/KALM. |