| Title |
High-speed DCT Circuit for Real-time 3D-HEVC Depth Map Encoder |
| Authors |
조경순(Kyeongsoon Cho) ; 권용욱(Yongwook Kwon) |
| DOI |
https://doi.org/10.5573/ieie.2020.57.4.42 |
| Keywords |
DCT; Real-time encoder; Intra coding; Depth map; 3D-HEVC |
| Abstract |
This paper presents the target performance of DCT circuit required for the real-time intra coding of UHD depth map which is usually decomposed into various PU sizes in 3D-HEVC, and proposes the architecture of high-speed DCT circuit to meet the target performance. In the process of intra coding of depth map, the candidate modes up to 13 are selected per PU and the DCT is performed for each mode. The RD cost is estimated based on the DCT results and the best mode is finally determined. In case of using pipeline techniques to improve the performance of the circuit, the latency should also be considered. Reflecting all these conditions, the target performance of DCT circuit is 4.63 GPPS for the real-time processing of 3,840x2,160 UHD images. The performance of the proposed circuit in this paper is improved by using butterfly, parallel, pipeline architectures, and especially the transpose memory based on the shift registers for the systematic data inputs and outputs. The throughput of the synthesized circuit using 130nm standard cell library is 5.31 GPPS for each of 4×4, 8×8, 16×16, 32×32 DCT types, which satisfies the target performance of 4.63 GPPS required for the real-time 3D-HEVC depth map encoder. |