| Title |
Timing Error Recovery Technique in a Single Cycle for Network-on-Chip Router |
| Authors |
강민구(Min Gu Kang) ; 강주연(Ju Yeon Kang) ; 이조은(Jo Eun Lee) ; 한태희(Tae Hee Han) |
| DOI |
https://doi.org/10.5573/ieie.2020.57.5.45 |
| Keywords |
Network-on-chip; Manycore architecture; Timing error; Error recovery; Pipeline architecture |
| Abstract |
In network-on-chip (NoC) -based manycore computing architectures, the probability of timing errors is rapidly increasing due to voltage variations and crosstalk noise caused by device down-scaling. Conventional double sampling-based timing error recovery techniques did not consider characteristics of network-on-chip routers that operate by referring to the data in the buffer, resulting in excessive power and area overhead of the recovery circuit. In this paper, we propose an NoC router which is capable of correcting timing error due to temporary and permanent defects in pipelined NoC routers in a single cycle by referring to buffer data. Based on a key observation that an NoC router maintains the data of the input buffer until the allocation stage, an error detection circuit is deployed in parallel with the routing operation elements to achieve the timing error recovery within a single cycle as well as reduced area overhead. Compared with the conventional timing error correction router using double sampling, the proposed design reduces the area and latency by 1.5 % and 33.4 % on average, respectively. |