| Title |
Design and Implementation of an Efficient Polar Decoder Supporting Simplified Successive Cancellation Algorithm |
| Authors |
김진원(Jin-won Kim) ; 김태환(Tae-Hwan Kim) |
| DOI |
https://doi.org/10.5573/ieie.2020.57.7.15 |
| Keywords |
Polar Code; Simplified Successive Cancellation Decoding Algorithm; Instruction Set; Pipeline; FPGA |
| Abstract |
This paper presents an efficient polar decoder architecture supporting the simplified successive-cancellation algorithm. The overall decoding procedure is decomposed into several instructions, for which an instruction-set architecture has been designed. An efficient decoder architecture is designed based on a 5 stages pipeline to execute the instructions. A 32,768bit polar decoder has been designed based on the proposed architecture and implemented using 6,121 LUTs in Intel Stratix IV FPGA. It achieves the decoding speed of 412 Mbps for the rate 0.84 code when operated at 144 MHz. |