| Title |
A Counter and VCO based DCPWM CMOS Buck Converter |
| Authors |
양홍렬(Hong Rouel Yang) ; 윤광섭(Kwang Sub Yoon) ; 이종환(Jong hwan Lee) |
| DOI |
https://doi.org/10.5573/ieie.2020.57.10.17 |
| Keywords |
CMOS; PMIC; DCPWM; Buck; Time-domain |
| Abstract |
The proposed DCPWM(Digital Controled Pulse Width Modulation) CMOS buck converter in this white paper is designed based on the voltage control oscillator and counter circuit of the digital control block. The analog signal contained in the input voltage was converted to a digital signal using a voltage-controlled oscillator that is less affected by voltage fluctuations even when the input voltage is lowered. Set generators and reset generators are designed using state generators to synchronize all blocks of the proposed circuit with the clock. A method of counting time, a method of detecting a signal of a PFD(Phase Frequency Detector) without using an integrator, was used. The proposed DCPWM buck converter is designed using CMOS 65nm 6-metal 1-poly process. As a result of measuring the chip performance using a 2.2μH inductor and a 10μF capacitor as an external device, the input voltage range is 1.1V to 1.3V, the output voltage range is 0.3V to 0.6V, the load current range is 50mA up to 200mA, the output voltage ripple Is 60mV, switching frequency is 2MHz, and maximum power efficiency is 91%. The proposed buck converter is expected to be used for power management of mobile and wearable devices. |