| Title |
Design of High-performance Circuit for Variable Block-size SATD Computation |
| Authors |
조경순(Kyeongsoon Cho) ; 원지희(Jihee Won) |
| DOI |
https://doi.org/10.5573/ieie.2021.58.5.20 |
| Keywords |
SATD; Hadamard transform; Intra prediction; HEVC; VVC |
| Abstract |
This paper presents the target performance of SATD computation circuit required for the real-time intra prediction of the image which is decomposed into variable-size PU blocks in video encoding, and proposes the circuit architecture to meet the target. For the intra prediction of 3,840×2,160 4K UHD image at the speed of more than 30 FPS, the required minimum performances of SATD computation circuit are 8.7 GPPS and 21.6 GPPS in case of HEVC with 35 modes and VVC with 87 modes, respectively. The proposed circuit adopts the parallel architecture utilizing the butterfly module as a basic element. Eight butterfly modules are used for 4×4 Hadamard transform and 16 butterfly modules are used for 8×8 Hadamard transform. Since the proposed circuit includes four 4×4 Hadamard transform modules and one 8x8 Hadamard transform module, it processes 64 pixels per cycle for all PU types. The throughput of the synthesized circuit using 65nm standard cell library is 32 GPPS for each of 4×4, 8×8, 16×16, 32×32 SATD computation, satisfying the target performance required for the real-time video encoder. It also shows the better area versus performance characteristics, compared with other circuits to implement SATD computation. |