| Title |
High-level Synthesis Design and Implementation of an Efficient Capsule Network Inference System in an FPGA |
| Authors |
양해찬(Hae-Chan Yang) ; 박상준(Sang-Jun Park) ; 박관영(Kwoan-Young Park) ; 사재현(Jae-Hyun Sa) ; 김태환(Tae-Hwan Kim) |
| DOI |
https://doi.org/10.5573/ieie.2021.58.11.39 |
| Keywords |
Inference system; Capsule network; FPGA; High-level synthesis; Artificial intelligence |
| Abstract |
Capsule Network (CapsNet) models are known to be feasible for the robust image classifications, inherently having equivariance characteristics. However, its high computational workload involved in the inference algorithm hinders an efficient implementation. This study proposes an efficient CapsNet inference system in a resource-limited FPGA. The inference algorithm has been optimized for the fixed-point arithmetics. The complicated arithmetic operations such as the division and square-root have been eliminated effectively by modifying the activation functions. In addition, dedicated hardware components to perform time-critical steps have been designed and integrated. The proposed system has been implemented in Intel Cyclone V FPGA with 6348 ALMs, 163K-bit BRAM and 3 DSPs. The proposed system shows 193× faster inference speed, compared to the software implementation, achieving 2.35 GOP/s/DSP. |