||A Low Power 3rd-order Delta-Sigma Analog to Digital Converter with Gain Calibration for Sensor Applications
||진주환(Joohwan Jin) ; 채형일(Hyungil Chae)
|| Analog-to-digital converter(ADC); 3rd Delta-Sigma ADC; Inverter based amplifier; Double sampling; Gain calibration
||In this paper, a third-order low-power Delta-Sigma Analog-to-Digital Converter with low-power operation and Gain Calibration is designed. A 3rd order Delta-Sigma Analog-to-Digital Converter is constructed, and an Inverter based Amplifier is used for low power operation. In addition, higher power efficiency is obtained at the same Sampling rate by using the Double Sampling technique for low-power operation. Inverter based Amplifier is sensitive to PVT Variation and Common mode Voltage Variation of Input, so it solves this problem by adding Gain Calibration, LDO (Low Drop-Out regulator) and CMFB (Common Mode Feedback) circuit. The proposed circuit was implemented in a 180nm CMOS process. As a result of the PSD (Power Spectrum Density) graph, it was confirmed that SNDR was measured at 77.45 dB, ENOB was 12.57 bit, and total power consumption was 27.92 uW.