| Title |
Design of High-performance Unified DST-7/DCT-8 Circuit for Video Encoding based on H.266/VVC |
| Authors |
권용욱(Yongwook Kwon) ; 조경순(Kyeongsoon Cho) |
| DOI |
https://doi.org/10.5573/ieie.2022.59.1.10 |
| Keywords |
VVC; Transform; DST-7; DCT-8; Bit-plane |
| Abstract |
The most recent video compression standard H.266/VVC adopted the transform technique to support more various PU block sizes compared to the previous H.265/HEVC and added new transform kernels DST-7 and DCT-8 in addition to DCT-2. It also incorporated the MTS technique to select one of the three transform kernels and ZO technique to make some transform coefficients into all zeros. Because of these changes, the improved compression efficiency is achieved but the computational complexity is greatly increased. This paper proposes the high-performance unified architecture of DST-7/DCT-8 circuit including all these techniques based on H.266/VVC standard. The proposed circuit utilizes the adder-shifter structure based on bit-planes for the efficient implementation of DST-7 and DCT-8 whose computational complexity is higher than DCT-2. It utilizes a parallel structure, two-stage pipelines and the transpose buffer based on shift registers to improve the circuit performance. This circuit processes 64 residual data per cycle. The gate-level circuit synthesized using 65nm standard cell library shows the throughput performance of 32 GPPS for all PU block sizes at the maximum operating frequency of 500MHz. |