| Title |
Erase Modeling of Charge Trap Flash Cells and Its Application to Trap Energy Extraction of Dielectric Thin Films |
| Authors |
김건웅(Geon Woong Kim) ; 백승재(Seung Jae Baik) |
| DOI |
https://doi.org/10.5573/ieie.2022.59.1.104 |
| Keywords |
NAND flash; Charge trap flash; Erase modeling; Trap energy; Hafnium oxide |
| Abstract |
For scaling of NAND flash, it is necessary to develop not only stacking technology but also scaling technology for charge trap flash (CTF), which is a unit memory cell. The scaling direction of the charge trap flash is expected to consist of the development of new materials such as high-k dielectric films, and in this study, presents a simulation model of the erase operation of a charge trap flash cell to which a high-k thin film is applied. This model uses the average trap distance, drift velocity, and carrier lifetime to intuitively and easily understand the movement of charges injected into the trap layer.The trap energy, which is a major parameter of the trap layer, can be extracted by comparing the simulation results and experimental measurements in the CTF capacitor devices. The electron/hole trap energies of the trap layer obtained from the analysis of the simulation results were Si3N4(1.42, 0.93 eV), HfO2_amorphous(1.00, 1.13 eV), HfO2_polycrystalline(1.10, 1.14 eV), respectively. |