| Title |
Binary Graph Node Classification Datasets for Digital Logic Circuit Recognition |
| Authors |
권규안(Kyuahn Kwon) ; 정재용(Jaeyong Chung) |
| DOI |
https://doi.org/10.5573/ieie.2022.59.5.19 |
| Keywords |
Deep learning; Machine learning; Circuit recognition; Datasets; Static timing analysis |
| Abstract |
There are many studies on machine learning-based EDA tool automation. However, the dataset used in this kind of study was not disclosed. Due to the absence of a standard dataset for circuit recognition, it is difficult to evaluate and compare between different methods, therefore it is necessary to have a good benchmark dataset. Our aim is to propose a graph structure-based machine learning dataset for circuit recognition that can be applicable in machine learning. It is expected that the newly constructed dataset will provide an opportunity for advanced future research on circuit recognition. To verify the effectiveness of the constructed dataset, we define two supervised learning problems: predicting slack improvement by changing cell size or swapping fan-in. The circuit topology is modeled in the form of a graph representation to better capture the circuit information. For validity, we leverage a recent technique from graph convolution neural network to train a model and evaluate it on different test set splits. As a result, it was shown that the accuracy of both tasks is more than 90% accuracy and roc-auc value. It demonstrates the possibility of using a graph-based machine learning dataset for circuit recognition. The dataset is freely available at: https://github.com/jaeyongchung/OpenSTA |