| Title |
Offset Reduction Scheme of the Voltage Latched Sense Amplifier |
| Authors |
김동영(Dong-Yeong Kim) ; 김건(Geon Kim) ; 박진효(Jin-Hyo Park) ; 김수연(Su-Yeon Kim) ; 박제원(Je-Won Park) ; 이명진(Myoung-Jin Lee) |
| DOI |
https://doi.org/10.5573/ieie.2022.59.6.32 |
| Keywords |
Offset voltage; Sensing margin; Sense amplifier; Sensing fail; Memory |
| Abstract |
It is important to reduce the offset of the sense amplifier for the development of low power and high memory semiconductors. In this paper, we propose a Separated Driving-node Sense Amplifier (SDSA) to reduce the sensing failure rate by offset. As a method of separating a drive line in a conventional VLSA, the sensing failure rate in the same area at a low voltage of 0.9V is reduced by 70% or more. Moreover, the effect of reducing the sensing failure rate by increasing the area is increased by 15% or more. |