| Title |
Structural Optimization of BNN Accelerator Design for Memory Reduction and Low Power |
| Authors |
차준원(Jun Won Cha) ; 김영민(Youngmin Kim) |
| DOI |
https://doi.org/10.5573/ieie.2022.59.8.22 |
| Keywords |
Binarized neural network; XNOR; Shift operation; Hardware accelerator; Vivado; Verilog |
| Abstract |
Neural networks require a lot of data movement and computation. There is a limit to moving a lot of data at once in hardware, and an efficient method was needed. In order to reduce data movement and computation in hardware, there is a Binarized Neural Networks (BNN) model that binarizes input data and introduces bit-level XNOR and shift operation. In this paper, we propose a more improved optimized model using the basic BNN model based on the MNIST, Cifar10, and Cifar100 datasets. By analyzing the BNN algorithm structure, the number and location of layers can be optimized. The BNN structure optimization model proposed in this paper showed great advantages in memory usage and power consumption, while maintaining similar accuracy to the existing experimental results. The proposed optimization model was implemented through Verilog of Vivado 2020.2 and experimentally verified using the latest dataset. As a result of the experiment, the proposed structure reduced the number of LUTs by 26.7% and power consumption by 44.1% compared to the existing structure. |