| Title |
Design of A Reconfigurable Low Power High Resolution Hybrid Analog to Digital Converter |
| Authors |
강민성(Min-seong Kang) ; 윤광섭(Kwang S. Yoon) |
| DOI |
https://doi.org/10.5573/ieie.2022.59.9.23 |
| Keywords |
Reconfigurable; Hybrid; SAR; SS; ADC |
| Abstract |
This paper describes a CMOS reconfigurable hybrid ADC with high resolution for bio-signal processing. The proposed hybrid ADC consists of two exclusive parts, namely SAR architecture for MSB and Single Slope architecture for LSB. The reconfigurable capability was implemented by employing a timing block which includes reset generator, control circuit, binary counter, and bit detection circuit. The bit detection circuit driven by an external signal was able to reconfigure resolution (11 ~ 14-bit) of the proposed ADC. The proposed ADC was implemented with a standard CMOS 28nm 1-poly 8-metal process. The active layout area occupied 1700um x 500um. The simulation results demonstrated power consumption of 81.8 uW(analog and digital power of 17uW and 64.8uW), ENOB of 13.3-bit, DNL/INL of 0.7LSB and 0.8LSB, and FoM of 16.3 fJ/step. |