| Title |
A CMOS Charge Pump Circuit with Adjustable Output |
| Authors |
배성훈(Sung Hoon Bae) ; 강보성(Bo Seong Kang) ; 장형준(Hyeong Jun Jang) ; 김영기(Young Gi Kim) |
| DOI |
https://doi.org/10.5573/ieie.2022.59.9.41 |
| Keywords |
PLL; Charge pump; Phase frequency detector |
| Abstract |
In this paper, we propose an Integrated CMOS CP (Charge Pump) circuit with an inserted resistor between the CP circuit and ground to enhance the output voltage greater than the output pulse amplitude voltage generated by the internal switch control circuit. The main purpose of the proposed circuit is to provide an increased control voltage to VCO (Voltage Controlled Oscillator) in PLL (Phase Locking Loop) system, disregarding the complicated active LPF (Low Pass Filter) circuitry by simple insertion of the resistor. The proposed CP circuit has been designed and fabricated based on theoretical analysis and simulation. The fabricated 0.65 nm-COMS-process-based die has been measured with two signal generators. The resulting data from the analytic calculation, simulation and measurement are verified for the PLL system design application. As a result of the measurement, the proposed CP cicuit with the inserting resistor of 7.15 kΩ shows average output voltages of 2.09 V and 3.34 V, which are 12 times and 20 times higher, respectively, than the maximum traditional internal circuit value of 160 mV, when DC supply voltage of 3 V and 4.45 V, respectively, are applied. The proposed circuit idea is verified by PLL system experiment with the fabricated die resulting locked output signal at 1168.82 MHz with DC supply voltage of 4.5 V. |