| Title |
Efficient Regular Expression Pattern Matching Processor Architecture for Network Intrusion Detection Systems |
| Authors |
서병석(Byung-Suk Seo) ; 김은원(Eun-won Kim) |
| DOI |
https://doi.org/10.5573/ieie.2022.59.9.121 |
| Keywords |
Network intrusion detection system; Regular expression; Pattern matching; Special-purpose processor |
| Abstract |
With the rapid increase in Internet use, network intrusion detection systems (NIDS) are widely used, and hardware-based pattern matching is used when high-performance real-time processing is required. Processor-based pattern matching processors ReCPU, SMPU, and REMP have been proposed to solve the problem of the hardware-based method that requires resynthesis whenever a pattern is updated. However, these processor-based pattern matching processors inefficiently handle iterative operations of regular expressions. In this paper, we propose a regular expression matching processor architecture capable of efficient iterative operation by adding a new instruction to REMP and adding an iterative operations counter logic block to improve the inefficient iterative operation of ReCPU and SMPU. In particular, the inefficient method of processing a short sub-pattern as a repeat operation of the OR (|) instruction has been improved so that it can be processed as a single instruction. The proposed regular expression pattern matching processor was designed with Verilog and synthesized with Intel Stratix IV FPGA to verify its operation. |