| Title |
A Two-stage Pipelined Processor Architecture for Regular Expression Pattern Matching in NIDS |
| DOI |
https://doi.org/10.5573/ieie.2022.59.9.127 |
| Keywords |
Regular expression; Pattern matching; Special-purpose processor; Network intrusion detection system |
| Abstract |
Regular expression pattern matching used in applications such as computer virus vaccine, network intrusion detection systems and DNA sequence analysis is a computational intensive task. To satisfy the performance requirements, hardware-based solutions have been proposed. Several processors for regular expression pattern matching have been proposed to solve the lack of flexibility in full hardware solutions. However, they are still inefficient in matching multiple regular expression patterns and repetition operations in their instruction set are also inefficient. In this paper, we propose a two-stage pipelined processor architecture that can match input data streams with multiple regular expression patterns at line-rate and efficiently process repetitive patterns. The proposed architecture has a pipelined architecture combined with Cuckoo hashing for efficient multiple pattern matching. It is designed using verilog for verification and synthesized on an Intel Stratix IV GX FPGA. It can match hundreds or thousands of regular expression pattern up to 5.03 Gbps. |