| Title |
V-shaped Nanosheet FET for PMOS Performance Enhancement |
| Authors |
정기욱(KiWook Jung) ; 우상민(SangMin Woo) ; 정현준(HyunJoon Jung) ; 김소영(SoYoung Kim) |
| DOI |
https://doi.org/10.5573/ieie.2022.59.10.57 |
| Keywords |
V-shaped nanosheet FET(VNSFET); Nanosheet FET(NSFET); TCAD; Surface orientation |
| Abstract |
In this paper, we propose a v-shaped nanosheet FET (VNSFET) device architecture that can boost PMOS current for the development of the 3-nm node and beyond logic devices. In VNSFET, only PMOS forms the v-shaped channel while NMOS preserves the NSFET's structure. On the (100) wafer, v-shaped channel formed at 45-degree angle has (110) surface orientation, which improves hole mobility and increases current in comparison to the (100) channel. The v-groove structure is expected to be created by anisotropic wet etch with selectivity on the (110) plane. In the TCAD simulation, VNSFET increased PMOS current by 54% compared to NSFET. In the SPICE simulation of the ring oscillator, delay was reduced by 26%. Dynamic power consumption was decreased by 27% at the same performance, and performance was increased by 16% at the same power consumption. |