| Title |
Process Integration of Vertical Field Effect Transistors for Floating Gate FET |
| Authors |
정인우(In Woo Jeong) ; 백승재(Seung Jae Baik) |
| DOI |
https://doi.org/10.5573/ieie.2023.60.5.10 |
| Keywords |
Vertical FET; Floating gate; Logic gate; Polycrystalline Si channel; HfO2 tunnel barrier |
| Abstract |
This paper deals with the integration process and characterization of vertical field effect transistor (VFET) that constitutes floating gate field effect transistor (FGFET). In the process of integrating VFET, an ultrathin amorphous Si channel is proposed and a thin tunnel barrier between source/drain and the channel is proposed. The VFET manufactured in this study shows high threshold voltage, subthreshold swing (SS), and low on/off ratio. The reason for this is the parasitic capacitance of the tunnel barrier. In addition, the interface of the tunnel barrier that was not uniformly deposited, the grain boundary and the interface of the polycrystalline silicon channel were also affected by the charge trapping. |