| Title |
Design Optimization Technology for Decimation Filter for High Performance Sigma-delta ADC |
| Authors |
박상보(Sang-Bo Park) ; 김형원(Hyung-Won Kim) |
| DOI |
https://doi.org/10.5573/ieie.2023.60.5.17 |
| Keywords |
Decimation filter; CIC filter; Butterworth filter; Overflow; IIR filter |
| Abstract |
This paper presents a detailed design of a multistage Butterworth Decimation Filter, a class of Infinite Impulse Response (IIR) filters, for the sampling rate reduction. A new technique for detecting and preventing overflows in each stage is also illustrated, which allows for minimizing the register width of the filter implementation while maintaining a high Signal-to-Noise and Distortion Ratio (SNDR). We employ the Canonical Signed Digit (CSD) representation of the filter coefficients, which eliminates the need for multipliers and reduces the storage for filter implementation, thus making it an economical alternative to conventional implementations of IIR filters. We demonstrate with simulation results that the proposed Butterworth decimation filter and its performance, when integrated with a Sigma-delta ADC, can significantly improve the SNDR in the frequency range of interest compared to a conventional Cascaded Integrator Comb (CIC) filter. |