| Title |
A Low-power Reconfigurable Neural Interface Analog Front-end IC with Common-mode Artifact Cancellation Loop |
| DOI |
https://doi.org/10.5573/ieie.2023.60.6.28 |
| Keywords |
Analog front-end; Common-mode cancellation loop; Programmable gain amplifier; Narrow band buffer |
| Abstract |
This paper presents a low-power and low-noise analog front-end (AFE) for conditioning of neural signals. The proposed AFE consists of a low-noise amplifier (LNA) and a programmable gain amplifier (PGA), and also includes a common-mode cancellation loop (CMCL) circuit that can withstand large common-mode artifacts generated from the stimulator part of the neural interface. The CMCL circuit is controlled by comparators and logic gates to operate only when a large common-mode input is received. The proposed PGA is capable of additional gain adjustments of 1, 2, 5, and 10 times to amplify very small neural signals. In addition, the PGA is designed to have constant bandwidth regardless of additional gain adjustment. Since neural signals have different frequency bands, the proposed circuit is designed to enable recording by discriminating between action potential (AP) and local field potential (LFP) signals by controlling the bandwidth using a narrow band buffer. The high-pass cutoff frequency is adjustable between sub-1Hz and 500 Hz, and the low-pass cutoff frequency is adjustable from 290 Hz to 12 kHz. The voltage gain of the entire proposed AFE is 40 dB-60 dB, and the input referred noise (IRN) of 1.92 μVrms is achieved when CMCL is not operating in the 1-12 kHz band, while the IRN is 3.2 μVrms when CMCL is enabled. The total power consumption of the proposed AFE is 2.6 μW, and it is designed using a 0.18-μm CMOS process. |