| Title |
Area-efficient Partially-parallel FWHT Processor for OFDM/CDMA Communication |
| Authors |
황지우(Jiwoo Hwnag) ; 황용택(Youngtaek Hwang) ; 김민수(Minsu Kim) ; 유호영(Hoyoung Yoo) |
| DOI |
https://doi.org/10.5573/ieie.2023.60.11.72 |
| Keywords |
Fast walsh hadamard transform; Folding transformation; OFDM processor; CDMA processor |
| Abstract |
In this paper, we propose a Fast Walsh Hadamard Transform (FWHT) processor design method for Orthogonal Frequency Division Multiplexing (OFDM)/Code Division Multiple Access (CDMA) communication. This method enables intuitive design deduction compared to conventional methods and offers both area efficiency and low hardware complexity. Existing design methodologies have not been able to solve the trade-off problem between hardware complexity and computational throughput in limited hardware resources. We propose a partially parallel FWHT processor design technique to solve this problem. The proposed partially parallel FWHT processor utilizes the folding transformation technique to perform the data rearrangement process more efficiently and enables a more intuitive structure derivation compared to existing design techniques. This paper also presents the results synthesized in the CMOS 180nm process, and confirms that the proposed partially parallel FWHT processor structure occupies 88% less area than the fully parallel structure and shows 405% higher throughput than the serial structure. Additionally, it was confirmed that the proposed design technique shows flexible and efficient performance in various hardware environments. This shows that it can contribute to improving the performance of OFDM and CDMA based wireless communication systems. |