| Title |
A Static Contention-free Topologically Compressed Flip-flop for Low Power and Low Voltage Operation |
| Authors |
강경훈(Kyounghun Kang) ; 정완영(Wanyeong Jung) |
| DOI |
https://doi.org/10.5573/ieie.2023.60.11.111 |
| Keywords |
Flip-flop; Near-threshold voltage; Contention; Low power; Toplogically compression method |
| Abstract |
The conventional topologically-compressed flip-flop (TCFF) achieves high energy efficiency by reducing the data activity ratio of internal nodes and minimizing transistor counts. However, it suffers from a race condition that it can lead to functional failure when operating at near-threshold voltage (NTV) levels. By resolving this issue, the presented flip-flop (SCTCFF) can operate down to 0.3V without power loss. In a test circuit of FFs utilizing 65nm CMOS process shows that SCTCFF saves 44.4% / 39.0% power compared to TGFF with 10% / 20% activity at 1V. |