| Title |
Design of High-performance Radial Distortion Correction Circuit for Real-time Processing of UHD Images |
| Authors |
황준상(Junsang Hwang) ; 조경순(Kyeongsoon Cho) |
| DOI |
https://doi.org/10.5573/ieie.2023.60.12.3 |
| Keywords |
Lens distortion correction; Backward mapping; Interpolation; Cache; UHD image |
| Abstract |
This paper proposes an architecture of a high-performance radial distortion correction circuit that processes UHD images in real time. In previous research, a method of directly accessing the entire image in memory at every clock cycle is commonly employed when accessing the image data necessary for distortion correction. However, this approach becomes impractical when dealing with high-resolution images due to the limitations of internal memory capacity. Even if storing the entire image in external memory, accessing external memory at every clock cycle for real-time processing in the actual application context remains nearly infeasible. To address this issue, the circuit architecture proposed in this paper introduces the concept of caching. The architecture pre-stores the image pixel values that need to be accessed in cache memory, significantly reducing the frequency of external memory accesses. As a result, it becomes possible to handle real-time high-resolution image processing, such as UHD images. The cache memory is implemented using 362K-bit SRAM. The results synthesized using a 65nm standard cell library show that the circuit comprises 29,667 gates, achieves a maximum operating frequency of 1,200MHz, and processes 4K UHD images at a speed of 0.3 GPPS, meeting the performance requirements for real-time processing. |