| Title |
Low-power and Reliable Operation 16-transistor Single-phase Clocked Flip-Flop in NTV |
| Authors |
석준하(JunHa Suk) ; 김혜선(Hyeseon Kim) ; 김소영(SoYoung Kim) |
| DOI |
https://doi.org/10.5573/ieie.2024.61.2.58 |
| Keywords |
Flip-Flop (FF); Near-threshold voltage (NTV); Static; Contention |
| Abstract |
In this paper, we propose a new low-power 16-transistor single-phase clock (16TSPC) flip-flop (FF) that can operate reliably in the near-threshold voltage (NTV) region. The 16TSPC is designed to completely eliminate contention and enable fully static operation. Therefore, the dynamic power consumption of the FF is reduced, and it can operate stably in the NTV region without operation errors caused by process variations. In addition, since it operates stably without operation errors, it is possible to operate over a wide range of operating voltages (1V to 0.3V). Then, to verify the performance and reliability of the 16TSPC in the NTV region, simulations were conducted using a 28nm process design kit (PDK). We compared the power consumption, CLK-to-Q delay, power delay product (PDP) and layout area of the proposed 16TSPC with respect to other designs. Also to test the reliability, we performed the Monte-Carlo simulations and compared the results with those of conventional designs. |