| Title |
Sub-3nm Standard Cell Performance and Power Evaluation using Buried Power Rail |
| Authors |
이충목(Choongmok Lee) ; 이승환(Seunghwan Lee) ; 석준하(JunHa Suk) ; 김소영(SoYoung Kim) |
| DOI |
https://doi.org/10.5573/ieie.2024.61.3.29 |
| Keywords |
Sub-3nm standard cell design; Buried power rail(BPR); Logic 3nm parasitic RC |
| Abstract |
This paper presents a quantitative characterization of BPR(Buried Rower Rail) cells for the development of logic sub-3nm standard cells. It involves the construction of a compact model based on BSIM-CMG that reflects the characteristics of NSFET and utilizes a 3D numerical field solver for accurate extraction of parasitic components. The analysis shows that in a 3nm standard cell, parasitic components have a greater impact on circuit performance than intrinsic components of the device, which emphasizes the importance of local interconnects to interconnect devices within the cell in the MOL region. The power and performance analysis also shows that the Via to Buried Power Rail (VBPR), which connects the buried power rail to the active contact (M0), is a key design element critical to performance, and suggests an optimal performance design of VBPR. Furthermore, this paper emphasizes that parasitic capacitance has a more substantial influence than resistance by analyzing parasitic components. Consequently, to reduce the primary component of parasitic capacitance, we explore the effects of gate extension scaling and present approaches for performance and power optimization based on the barrier-less M0 CD(Critical Dimension). |