| Title |
A Design and Implementation of 32-bit RISC-V RV32IM Processor based on Dynamic Branch Prediction |
| Authors |
박수빈(Subin Park) ; 김용우(Yongwoo Kim) |
| DOI |
https://doi.org/10.5573/ieie.2024.61.10.118 |
| Keywords |
RISC-V; Processor; 5-stage pipeline; Branch prediction; FPGA |
| Abstract |
The RISC-V ISA, which has been actively researched and utilized in recent years, is a RISC-based open instruction set architecture(ISA) that has been developed at UC Berkeley since 2010. RISC-V has the RV32I ISA as its base instruction set, which includes instructions for memory access, integer arithmetic, and branching, and the next extension to be considered after RV32I is the M-extension, which includes multiplication and division instructions. While processing the Branch-related instruction of the RV32IM ISA, failure to predict the branch incurs a penalty and causes a degradation in processor performance. In this paper, an RV32IM processor with gshare and RAS techniques among the dynamic branch prediction techniques has been designed, and the optimized size of the PHT included in the applied gshare technique has been identified. The maximum operating frequency of the proposed processor satisfies more than 50 MHz on the Artix-7 FPGA. The performance of the proposed processor is verified through Dhrystone and CoreMark benchmark programs. The proposed processor has a 1.35 DMIPS/MHz and 2.96 Coremark/MHz. From the equivalent result, the DMIPS score of the proposed processor performed 8% better than the RVCoreP processor, which is the high-performing processor from related studies. |