| Title |
Multi-layer Escape Routing Algorithm using Optimization Method |
| Authors |
조범근(Beom Geun Cho) ; 구형일(Hyung Il Koo) |
| DOI |
https://doi.org/10.5573/ieie.2025.62.1.43 |
| Keywords |
PCB; Escape routing; Layout; Optimization |
| Abstract |
In PCB (Printed Circuit Board) design, escape routing has become increasingly time-consuming and complex due to higher chip integration densities and an increased number of components, leading to active research in automation. Previous research either support only single-layer routing or assume simplified scenarios without constraints on the routing area, which limits their practical application in actual designs. In this paper, we propose an algorithm to efficiently perform multi-layer escape routing. The proposed algorithm can simultaneously handle escape routing for both single signals and differential pairs across multiple layers. Specifically, by considering the merge process where the two signals of a differential pair merge at a single node and the process where they are routed together, we achieve efficient routing results on multiple layers. Additionally, we propose a method to convert routing results represented at the graph level into PCB layouts. By defining the PCB layout conversion as an integer linear programming problem and formulating design conditions as constraints, we can generalize and handle a wider variety of conditions and input forms compared to previous research. The proposed method demonstrated a higher routing success rate on actual design data compared to previous research. Notably, because the positions of differential pairs can be adjusted and routed across multiple layers, we confirmed that more differential pairs can be routed even under challenging conditions. |