| Title |
Sequential Gate Merging Technique for Accelerating Quantum Circuit Simulation |
| Authors |
최승우(Seungwoo Choi) ; 장은혁(Enhyeok Jang) ; 김영민(Youngmin Kim) ; 노원우(Won Woo Ro) |
| DOI |
https://doi.org/10.5573/ieie.2025.62.3.29 |
| Keywords |
Quantum computing; Quantum circuit simulation; Quantum circuit compilation |
| Abstract |
Quantum circuit simulation plays a crucial role in verifying quantum hardware and software. It involves sequentially applying matrix operations corresponding to the gates in a given quantum circuit to an initial state vector representing the quantum state. To enable faster and more efficient simulation, a gate merging technique is employed, which combines adjacent gates into larger gates and performs the operations in a single step. The state-of-the-art quantum circuit simulator, Qulacs, provides a technique that checks the adjacency of all gate pairs in a circuit and merges them into gates with a number of target qubits that do not exceed a user-specified block size. However, this method of using a single block size for gate merging has a limitation: it merges gates too quickly as soon as the condition is satisfied, which increases the likelihood of missing better merging opportunities later in the circuit. To address this limitation, we propose a sequential gate merging technique that incrementally increases the block size while performing gate optimization. By using this approach, gates are merged progressively, enabling the simulation to achieve a smaller number of merged gates overall. Experimental results show that the proposed sequential gate merging technique achieves, on average, a 29.9% improvement in simulation speed compared to the peak performance of Qulacs on MQT benchmark circuits. |