| Title |
Design and Analysis of an Optimized Cache Structure based on 32-bit RISC-V RV32I using FPGA |
| Authors |
오호빈(HoBin Oh) ; 김용우(Yongwoo Kim) |
| DOI |
https://doi.org/10.5573/ieie.2025.62.4.27 |
| Keywords |
Cache; RISC-V; FPGA; Embedded system; SoC |
| Abstract |
Embedded systems predominantly use ARM-based Cortex-R and Cortex-M series microcontrollers, which often employ caches to achieve high performance. However, there is a lack of comprehensive analysis on the performance and energy efficiency of different cache structures and sizes specifically tailored for the RISC-V processor, a rapidly growing open-source architecture. To address this gap, this study implemented various cache structures (Direct Mapped Cache, 4-Way Set-Associative Cache, and Fully Associative Cache) as both instruction and data caches in a Embedded RISC-V-based 32-bit RV32I 5-stage pipeline processor. We evaluated these implementations using the Dhrystone and Coremark benchmark programs to determine the optimal cache structure and size. The designs were synthesized and implemented on the Artix-7 Nexys A7-100T FPGA board, targeting a maximum operating frequency of 50MHz. We analyzed hardware resource usage and verified FPGA operation. Based on benchmark scores, cache miss rates, and hardware resource usage, the optimal instruction cache was determined to be a 16KiB 4-Way Set-Associative Cache, while the optimal data cache was found to be a 4KiB 4-Way Set-Associative Cache. |