| Title |
The Study on FPGA Implementation of Metadata Table-based In-order RISC-V Processor for Heap Memory Vulnerability Detection |
| Authors |
박현재(Hyunjae Park) ; 강진구(Jin-Ku Kang) ; 김용우(Yongwoo Kim) |
| DOI |
https://doi.org/10.5573/ieie.2025.62.4.36 |
| Keywords |
Memory safety; RISC-V; Memory tagging; FPGA implementation |
| Abstract |
The RISC-V processor, developed at UC Berkeley as an open-source ISA, is widely used in embedded systems for its low power consumption and scalability. However, memory vulnerabilities persist due to unsafe programming languages like C/C++. This paper proposes a low-overhead hardware design for detecting heap memory vulnerabilities in an In-Order RISC-V processor. While In-Order processors are cost-effective and energy-efficient, their limited resources make implementing memory safety mechanisms challenging. To address this, we combine metadata tables and boundary checking to enhance memory safety with minimal performance loss. FPGA implementation on a VC707 board showed an average 13.08% execution time. Verification using the Juliet Test Suite demonstrated effective detection of double-free, use-after-free, and overflow vulnerabilities, confirming the proposed design’s efficiency in detecting heap memory vulnerabilities with minimal performance overhead. |