| Title |
A 4-times Interpolating Flash Analog-to-digital Converter based on Complementary Dynamic Amplifiers |
| Authors |
김한준(Han-Jun Kim) ; 오동렬(Dong-Ryeol Oh) |
| DOI |
https://doi.org/10.5573/ieie.2025.62.9.51 |
| Keywords |
Analog-digital converter; Flash ADC; Complementary dynamic amplifier; time-domain interpolation |
| Abstract |
High-speed Analog-to-Digital Converters (ADCs) are widely used in data communication and sensor applications. Among various ADC architectures, the flash ADC is most suitable for high-speed data conversion, as it performs a parallel conversion within a single clock cycle. However, as the resolution increases, the number of comparators increases by , which leads to increased input capacitance and power consumption. To address these drawbacks, we propose a 4-bit 20-MS/s flash ADC that incorporates Complementary Dynamic Amplifiers (CDAs) and a Time-Domain Interpolation (TDI) technique. This approach reduces the design burden of high-speed clock generators and dynamic latches. Additionally, by reducing the number of comparators through 4-times time-domain interpolation, we can improve both the input capacitance and power efficiency of the ADC. The proposed prototype ADC was implemented using a 500 nm CMOS process. It was confirmed that the input capacitance of the proposed 4-times interpolating flash ADC is improved by approximately 36.5%, with power efficiency improved by about 5% compared to that of a 2-times interpolating flash ADC. After offset correction, the Effective Number of Bits (ENOB) measured at the Nyquist input is 3.25 bits, the Signal-to-Noise and Distortion Ratio (SNDR) is 21.3 dB, and the Spurious-Free Dynamic Range (SFDR) is 32.47 dB. The total power consumption of the ADC is 15.63 mW, and the Walden Figure of Merit (FoMW) is calculated to be 82.1 pJ/conversion-step. |