| Title |
A Ripple-cancellation LDO with Sub-pass Transistor and VCDL for Clocking Circuits in 180nm CMOS |
| Authors |
김민균(Mingyun Kim) ; 송준영(Junyoung Song) |
| DOI |
https://doi.org/10.5573/ieie.2025.62.10.29 |
| Keywords |
Analog LDO; Capacitor-less; Low ripple; VCDL |
| Abstract |
This paper proposes a structure using a sub- pass transistor and reduced CLOAD to suppress LDO output ripple from clocking circuits. Implemented in 180nm CMOS, the VCDL-based LDO regulates 1.8V to 1.6V and achieves 46% ripple reduction. |