| Title |
Automated Deep Learning Accelerator Design for On-sensor Image Signal Processing |
| Authors |
원동언(Dong-eon Won) ; 최정욱(Jungwook Choi) |
| DOI |
https://doi.org/10.5573/ieie.2025.62.11.21 |
| Keywords |
Image signal processing; On-sensor deep learning acceleration; Automatic accelerator design |
| Abstract |
Deep neural network-based image signal processing (ISP-DNN) improves image quality with techniques such as demosaicing, but these models pose substantial computational and memory challenges when implemented on CMOS image sensors, particularly due to the high-resolution inputs that increase memory requirements for activations. Layer fusion reduces memory usage by combining consecutive processing steps, yet it increases the required number of compute units, a critical issue in resource-limited on-sensor environments. To address these challenges, we introduce ISP2DLA, an automated deep learning accelerator design framework that balances computational and memory demands for on-sensor ISP. This framework optimizes hardware designs by adjusting line buffer sizes and the number of MAC units, reducing gate counts by 14--79% across two ISP-DNN models, thus enabling efficient on-sensor ISP model inference within constrained resources. |