| Title |
A 15 bit Noise-shaping SAR ADC Design |
| DOI |
https://doi.org/10.5573/ieie.2026.63.2.15 |
| Keywords |
Dynamic amplifier; Mismatch error shape; Noise-shaping SAR; Data weighted average; Analog-to-digital converter |
| Abstract |
This paper presents a 15-bit energy-efficient noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC). The proposed architecture is based on a 12-bit SAR ADC augmented with a first-order FIR-IIR hybrid loop filter that shapes the quantization noise. The loop filter can leverages a dynamic amplifier, enabling robustness against process, voltage, and temperature (PVT) variations. Specifically, the design maintains an Signal-to-Quantization Noise Ratio (SQNR) of 107.8 dB even under ±30% gain variation. To mitigate linearity degradation caused by capacitor mismatch, the SAR ADC is split into most significant bit (MSB) and least significant bit (LSB) segments, and enhanced using data-weighted averaging (DWA) and mismatch error shaping techniques. With these techniques, the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 67.7 dB to 104.3 dB in MATLAB simulation. |