| Title |
An FPGA-based NTT Accelerator with a Unified Butterfly and Ping-Pong Memory Access |
| Authors |
김승찬(Seungchan Kim) ; 김정욱(Jeonguk Kim) ; 김동순(Dongsun Kim) |
| DOI |
https://doi.org/10.5573/ieie.2026.63.3.45 |
| Keywords |
Number theoretic transform; Lattice-based cryptography; Fpga implementation; Hardware accelerator |
| Abstract |
The Number Theoretic Transform (NTT) is a key operation that enables efficient polynomial multiplication and is widely used as the computational core of cryptographic systems such as post-quantum cryptography (PQC) and homomorphic encryption. This paper proposes an area?time efficient NTT hardware accelerator implemented on an FPGA. The proposed design employs a pipelined unified butterfly unit and an optimized modular multiplication scheme to effectively reduce memory bottlenecks and hardware overhead. In particular, a ping-pong dual-port BRAM access method is applied to double the effective memory bandwidth while enabling conflict-free data access and parallel processing using two pipelined butterfly units. Implementation results on a Xilinx Virtex-7 FPGA show that the proposed architecture utilizes 1,318 LUTs, 2,020 FFs, 9 DSPs, and 4 BRAMs. Compared with existing state-of-the-art designs, the proposed accelerator achieves the lowest area?time product (ATP) and improves efficiency by 1.05× to 3.16×. |