| Title |
Implementation and Verification of Probabilistic Computing System Based on Emulated Random Circuit Elements : A Basic Study |
| Authors |
최승혜(Seunghye Choi) ; 주현태(Hyuntae Ju) ; 설주화(Juhwa Seol) ; 주병권(Byeongkwon Ju) ; 홍석민(Seokmin Hong) |
| DOI |
https://doi.org/10.5573/ieie.2026.63.7.56 |
| Keywords |
p-bit; Probabilistic computing; Hardware emulation; Simulated annealing; Probabilistic logic |
| Abstract |
As Moore’s Law faces scaling challenges, probabilistic computing has emerged as a promising CMOS+X technology to efficiently solve complex optimization and NP-hard problems that are computationally expensive for traditional digital systems. In this study, we designed and experimentally verified a probabilistic computing system using p-bits based on stochastic device behavior. By emulating sMTJ (stochastic Magnetic Tunnel Junction)-like characteristics at the circuit level, we built a working p-bit network. Our results show that the relative tuning of sampling and retention time strongly affects system performance and stability, as validated through invertible full adder logic and 10-bit 3-SAT problem-solving tasks. |