| Title |
Design of (N, k) Parallel Counter for High-Speed Summation of Many Inputs |
| DOI |
https://doi.org/10.5573/ieie.2026.63.9.40 |
| Keywords |
Parallel counter; Multi-bit adder; Perceptron implementation; Modular parallel counter; Parallel counter circuit |
| Abstract |
An architecture of (N, k) parallel counter is presented in this paper. The new parallel counters called modular parallel counter are designed for applications requiring high-speed summation of many numbers. The summation process consists of several carry save addition (CSA) stages and a carry propagation addition (CPA) stage. Parallel counters reduce total execution time of all CSA stages (TCSA) by decreasing the number of CSA stages. Compared to the summation using full adders only, 41% of TCSA is reduced when adding 7 numbers by employing (7, 3) parallel counter, and 31% when adding 15 numbers by (15, 4) parallel counter. The new architecture has a modular structure so that it is easy to design parallel counters of any size. The circuits for counters ranging from (5, 3) to (15, 4) are presented. High-speed summation can be achieved by searching for the optimum configuration of CSA stages with these various size parallel counters. |