| Title |
Signal Integrity Analysis of a DDR4 Memory Test Board with a 3-W Wiring-spacing Rule |
| Authors |
(Tae-Hyung Yun) ; (Moonjung Kim) |
| DOI |
https://doi.org/10.5573/IEIESPC.2020.9.6.491 |
| Keywords |
Memory test board; Signal routing; Signal integrity; Power integrity; 3-W wiring-spacing rule |
| Abstract |
In this study, a double data rate fourth generation (DDR4) memory test board was designed with 3-W wiring spacing and compared against a board with 10-W spacing in terms of signal integrity and power integrity. Applying a 10-W wiring-spacing rule to the board design can reduce crosstalk between signal lines, improving signal quality, but also reduces the efficiency of the wiring area, resulting in an increase in the number of board layers. Therefore, in this study, efficient layer utilization and excellent signal quality are maintained in the board design and analysis stage while wiring signal traces at 3-W intervals. Simulations of the S-parameter, far-end crosstalk, power distribution network impedance, and eye-diagram of the board were performed to analyze the effect of signal quality due to changes in wiring spacing on board design. These results verify that the memory test board on which the 3-W wiring was applied is effective in obtaining a 3.2 Gbps operational speed and proper signal integrity. |