| Title |
Phase-locked Loop with True Random Number Generator for Reference Spur Reduction |
| Authors |
(Eojin Lee) ; (Seung-Myeong Yu) ; (Yunha Kang) ; (Junyoung Song) |
| DOI |
https://doi.org/10.5573/IEIESPC.2021.10.2.146 |
| Keywords |
Phase-locked loop; True random number generator; Reference spur |
| Abstract |
This paper presents a phase-locked loop (PLL) that reduces reference spurs by using a true random number generator (TRNG). In conventional PLLs, a frequency component of the reference clock appears spurious tones in the voltage-controlled oscillator (VCO) output. In the proposed PLL, the TRNG randomly delays UP/DOWN signals which result in inconsistent timing of charging/discharging at the output of the charge pump (CP). As a result, the CP output disperses the reference spur of the VCO output by making the reference clock frequency component uneven.
The proposed PLL was fabricated in a 180-nm CMOS technology. It dissipates 23 mW at 2-GHz with 1.8-V supply and achieves more than 23 dB of additional spur suppression. |