| Title |
Generation and Their Evaluation |
| Authors |
Moena Yamasaki(Moena Yamasaki) ; Akira Yamawaki(Akira Yamawaki) |
| DOI |
https://doi.org/10.5573/IEIESPC.2019.8.3.178 |
| Keywords |
High-level synthesis ; Histogram ; Image processing ; High performance ; Low power |
| Abstract |
To achieve high performance and low power simultaneously in an embedded image? processing product, hardware implementation of high computational?software processing is needed. Hardware development, however, is a large burden on the developer. High-level synthesis (HLS) for automatically converting software into hardware can significantly reduce the design burden. To use HLS technology efficiently, a software program must be described considering the hardware organization that the HLS tool will generate. Histogram generation is one of the important basic functions in image processing. In histogram generation, data dependency on reading and writing to the same address in the histogram hinders ideal pipelining by an HLS tool. |