3.1 Review of Existing CP Topologies

The Dickson topology is a popular and widely used CP architecture ^[6]. The n-stage Dickson CP is shown in Fig. 2(a), where the transistor devices act as diodes instead of switches. These diode-connected transistors are used to transfer or deliver charge from one stage to the next and has a simple architecture that can easily be combined with other standard CMOS circuits in a system. However, this topology has a drawback of degraded efficiency as more stages are added as the threshold V$_{\mathrm{TH}}$ rises due to the body effect, resulting in higher voltage drops. Several techniques to avoid the rise in threshold voltage due to the body effect have been developed to alleviate this issue ^[7], with added cost of complexity.

Fig. 2(b) shows the widely used cross-coupled latched CP circuit [5, 8, 9], in a two-stage configuration as an example. The cross-coupled latched CP has the advantage of achieving a reliable conversion operation at high voltage with reasonable efficiency. One drawback of this structure is that it uses two pumping switches in series at each stage, which leads to the conduction loss due to the larger switch on-resistance (R$_{\mathrm{ON}}$) than the topology that uses only one pumping switch in the current path.

Fig. 2. (a) Dickson charge pump, (b) Cross-coupled latched charge pump.

3.2 Proposed CP Core

Fig. 3 shows the proposed CP core circuit which employs the complementary CTS topology. The advantage of this circuit is that it employs a single transistor in each stage which leads to less conduction loss in comparison to the latched topology, which ultimately results in enhanced efficiency. Four stages are used to convert 3.2 V input to 15 V output. NMOS devices are used for the input stage switches and PMOS switches are used in the following stages in the core. To produce a large voltage output despite using 180 nm CMOS process, 3.3 V transistors are employed in the design. The switching transistors are sized with dimensions as shown in Fig. 3, which is decided considering in-rush current, R$_{\mathrm{ON}}$ value, and area. Inverters are utilized to control the ON-OFF of the PMOS switches. The source of the NMOS transistor in the inverter is connected to the previous stage node while the drain of the PMOS in the inverter is connected to the following stage node. Thus, the lower voltage from the previous stage is used to turn on the CTS switch, while the higher voltage in the following stage is used to turn it off.

The body terminal of the switches is connected to the dynamic body biasing (DBB) circuit for reliability purpose. This is used to connect the highest voltage between its source and drain for the PMOS transistor and the lowest potential for the NMOS transistor. As the input stage NMOS devices utilize deep n-well transistors, additional pairs of DBB circuits are used to ensure the n-well and the substrate are connected to the appropriate voltage.

The basic operation of the CP is described as follows. In the first stage, the charge passes through NMOS transistors SWN$_{1}$ and SWN$_{2}$ in the upper half and lower half branches of the cross-coupled structure, respectively. In the first cycle, when CLK$_{1}$ is low and CLK$_{2}$ is high, the voltage at node A$_{1}$ is close to V$_{\mathrm{IN}}$ and the voltage at node B$_{1}$ is about 2V$_{\mathrm{IN}}$. This causes the transistor SWN$_{1}$ to turn on and the charge gets transferred to capacitor C$_{1}$ from the input node. The voltage drop occurring across SWN$_{1}$ (V$_{\mathrm{DS}}$) is smaller than the threshold voltage. When CLK$_{1}$ is high and CLK$_{2}$ is low in the next clock cycle, the voltage at node A$_{1}$ becomes twice the V$_{\mathrm{IN}}$ while node B$_{1}$ decreases to around V$_{\mathrm{IN}}$, thus turning SWN$_{1}$ off and blocks the current path. SWN$_{2}$ operates similarly in the opposite way. After that, the charge will be passed through transistors SWP$_{1-6}$, where these switches are controlled using inverters. As the charge transfer operation of switch transistors SWP$_{1}$ to SWP$_{6}$ is similar, the second stage operation is described as an example. At this point, the voltage at the source node of SWP$_{1}$ is around 2V$_{\mathrm{DD}}$. To turn on and off SWP$_{1}$ using the lower voltage from the previous stage, both the NMOS and PMOS gates of the inverter INV$_{1}$ are connected to node A$_{1}$, the NMOS source of INV$_{1}$ is connected to B$_{1}$, and PMOS source of INV$_{1}$ is connected to node A$_{2}$. In contrast, the drain nodes of NMOS and PMOS devices are connected to the gate of SWP$_{1}$. Likewise for SWP$_{2}$, both NMOS and PMOS gates of inverter INV$_{2}$ are coupled to B$_{1}$, the NMOS source of INV$_{2}$ is connected to node A$_{1}$, and the PMOS drain of INV$_{2}$ is connected to node B$_{1}$, while the drain nodes of NMOS and PMOS devices are coupled to the gate of SWP$_{2}$. When CLK$_{1}$ is high, the SWP$_{1}$ switch turns off and cuts off the current path to the next stage. When the CLK$_{1}$is low, the SWP$_{1}$ turns on. The transistor SWP$_{2}$ works in a similar manner with CLK$_{2}$.

The last stage comprised of switches SWP$_{7}$ and SWP$_{8}$operates in a similar working principle as the first stage but uses the PMOS transistor instead of NMOS. At this point, the voltage level at the source node of SWP$_{7}$ and SWP$_{8}$ is around 5V$_{\mathrm{DD}}$. The gate terminal of SWP$_{7}$ is connected to B$_{\mathrm{4,}}$ while the gate of SWP$_{8}$ is connected to A$_{4}$. When CLK$_{1}$ is low, SWP$_{7}$is turned on while SWP$_{8}$ is turned off. The on-state of SWP$_{7}$ and SWP$_{8}$ allows transfer of charge from C$_{7}$ and C$_{8}$ to the output capacitor C$_{\mathrm{out}}$.

To generate the two-phase clock for driving the complementary branches, a non-overlapping clock signal generation circuit, shown in Fig. 4, is realized by combining NAND gate and inverters. A small delay is included to minimize the pumping transistors turning on and off simultaneously.

Fig. 3. Circuit schematic of proposed CP core.

Fig. 4. Non-overlapping clock circuit.

3.3 Regulation Scheme

The output voltage of a complementary CP circuit can be defined as:

where $V_{I{N_{-}}CP}$ represents the input of the CP, N is the number of stages, f$_{\mathrm{OSC}}$ is the pumping frequency, C$_{\mathrm{P}}$ is the pumping capacitor, and I$_{\mathrm{L}}$ is the load current. It can be observed from this equation that either $V_{I{N_{-}}CP}$ or f$_{\mathrm{OSC}}$ should be controlled for regulating the output V$_{\mathrm{O}}$ with a change in load current ^[4,10]. The issue of tuning the pumping frequency is that regulation may not be achieved at very light load condition as I$_{\mathrm{L}}$ ${\approx}$ 0. At heavy load condition where the pumping frequency is dynamically increased to pump more current to the output, there can be excessive switching loss due to the increased switching frequency which may degrade the overall efficiency of the CP. On the other hand, modulating the input voltage can be done with no limitations at both light and heavy loads with a fixed frequency for switching. The pumping frequency affects the efficiency as well as the output ripple voltage. A trade-off exists between these two parameters where a high clock frequency degrades the efficiency while it is favorable for the ripple performance. This work employs the input voltage modulation regulation method while using a fixed 100 kHz pumping frequency for minimizing the loss due to fast switching and achieve a reasonable ripple performance.

While employing the 1 ${\mathrm{\mu}}$F pumping capacitor, the appropriate $V_{I{N_{-}}CP}$ value can be calculated using equation (1). Two load conditions are considered where I$_{\mathrm{L}}$= 0 mA and I$_{\mathrm{L}}$ = 5 mA, which are minimum and maximum load conditions, respectively:

Now, the relationship between $V_{I{N_{-}}CP}$ and $V_{REF\_ LDO}$can be decided by the following equation:

where R$_{\mathrm{L1}}$ and R$_{\mathrm{L2}}$ are assumed to be the feedback voltage divider resistors in the output of the LDO circuit. Assuming R$_{\mathrm{L1}}$ = R$_{\mathrm{L2}}$, when $V_{I{N_{-}}CP}$varies from 3 V to 3.02 V from Eqs. (2) and (3), the $V_{REF\_ LDO}$value should fall between 1.5 V and 1.51 V in order to support the load current values between 0 to 5 mA. From this data, the reference voltage of EA ($V_{REF\_ EA}$) is set to 1.5 V.

Fig. 5 shows the simplified circuit schematic of the EA in the feedback regulation path, which performs the error comparison between voltage-divided output voltage V$_{\mathrm{FB}}$and the reference voltage. The voltage error is first converted to current $I_{Fb}$ using the operational transconductance amplifier (OTA) in the EA and then re-converted back to voltage output $V_{REF\_ LDO}$. The $V_{REF\_ LDO}$can be expressed as follows:

The general idea is that when the V$_{\mathrm{OUT}}$ of the CP does not exceed 15 V, then V$_{\mathrm{FB}}$ < $V_{REF\_ EA}$and OTA delivers $I_{Fb}$ to R$_{\mathrm{C}}$, increasing $V_{REF\_ LDO}$, which leads to the increase of $V_{I{N_{-}}CP}$and thus the increase of V$_{\mathrm{OUT}}$. When V$_{\mathrm{OUT}}$ exceeds 15 V, the OTA will sink $I_{Fb}$ from R$_{\mathrm{C}}$, thus decreasing $V_{I{N_{-}}CP}$and V$_{\mathrm{OUT}}$. The resulting output voltage generated is applied to the LDO in the feedforward input path as the LDO reference voltage. The output of the EA circuit also features a limiter (upper and lower limiters) to limit the voltage applied to the LDO at start-up of the CP when the error between the feedback V$_{\mathrm{FB}}$ and the reference $V_{REF\_ EA}$ is too large. This forces $V_{I{N_{-}}CP}$ to be within the range of 2.8 V to 3.1 V.

Fig. 6 shows the LDO used in this system. A conventional LDO circuit ^[5] is used with adjustments to enable a larger output voltage and load current. As shown, a PMOS pass transistor, a telescopic error amplifier, a buffer, and two feedback resistors are used in the LDO circuit. A similar limiter block used for the EA is also utilized in the LDO to limit the current in the pass transistor at start-up.

Fig. 5. Simplified circuit schematic of EA in the feedback regulation path.

Fig. 6. Simplified circuit schematic of LDO.